There is a conventional technique so-called non-uniform memory access (NUMA) that configures such a system that nodes are provided, each of the nodes has a processor and a memory, and the memory is shared between the nodes.
As a related conventional technique, for example, there is a technique of automatically extracting tasks having parallelism from an input program to be processed by a compiler, and arranging the tasks according to characteristics of processor units, in a multiprocessor system. There is also a technique of setting an arrangement having preceding reference data dependency to a work variable, generating a loop, and, after the loop, calculating an execution sentence of the loop where the arrangement having the data dependency is replaced with the work variable. There is also a technique of outputting a transaction for synchronization, after all the transactions of preceding instructions are outputted, to a main memory that serializes memory accesses by the transaction, and to a coherence unit that guarantees completion of cache coherence control by the transaction. There is also a technique of performing a barrier synchronization process, by allocating a synchronization flag area of each processor on a shared memory, updating the synchronization flag area with software in accordance with an execution condition, and causing each processor to compare the synchronization flag areas of other processors taking part in the barrier synchronization with each other. There is also a technique of generating an object code executable on a shared memory type computer with a thread as a unit of parallel processing, by using an intra-thread synchronization overhead information file and a number-of-machine-cycles acquisition library.
Known examples of the conventional techniques include Japanese Laid-open Patent Publication Nos. 2006-293768, 2010-191506, 2000-194680, 2005-71109, and 2007-108838.